General descriptions
In order to meet wide applications of embedded system, Andes provides three major CPU core families : N12 for high-end applications based on Linux, N10 for mid-range applications based on Linux and RTOS, N9 for low-end applications and MCU based products. The following list the key features for those three families
Vector interrupts for internal/external
interrupt controller with 6 hardware interrupt signals
3 HW-level nested interruptions User and super-user mode support Memory-mapped I/O Address space up to 4GB
Memory Management Unit
TLB 4/8-entry fully associative iTLB/dTLB 32/64/128-entry 4-way set-associative main TLB TLB locking support Optional hardware page table walker Two groups of page size support 4KB & 1MB 8KB & 1MB
Memory Subsystem I & D cache
Virtually indexed and physically tagged Cache size: 8KB/16KB/32KB/64KB Cache line size: 16B/32B Set associativity: 2-way, 4-way or direct-mapped Cache locking support
I & D local memory (LM)
Size: 4KB to 1MB Bank numbers: 1 or 2 Optional 1D/2D DMA engine Internal or external to CPU core
Bus Interface
Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports
Synchronous High speed memory port
(HSMP): 0, 1 or 2 ports
Flexibility Memory-mapped IO space PC-relative jumps for position independent code JTAG-based debug support Performance monitors for performance tuning Bi-endian Power Management Clock-gated pipeline Low-power mode support instructions
Applications
Digital TV Digital Home Set top Box MFP Switch/Router Communication Smart Phones
16/32bit mixable instruction format 32 general-purpose 32-bit registers 5-stage pipeline Dynamic branch prediction with 32/64/128-entry BTB Return address stack (RAS) Multiply-add and multiply-subtract instructions Post-increment aligned load/store single Aligned and unaligned load/store multiple Vector interrupts for internal/external interrupt controller with 6 hardware interrupt signals 3 HW nested interruption levels User and super-user mode support Memory-mapped I/O and up to 4GB address space
Memory Management Unit
TLB 4/8-entry fully associative iTLB/dTLB 32/64/128-entry 4-way set-associative main TLB TLB locking support Optional hardware page table walker Two groups of page size support 4KB & 1MB 8KB & 1MB
Memory Protection Unit
8 memory protection regions
Memory Subsystem I & D cache
Virtually indexed and physically tagged Cache size: 4KB to 32KB Cache line size: 16B/32B Set associativity: 2-way Cache locking support
I & D local memory (LM)
Size: 4KB to 64KB (Internal), up to 1MB (External) Bank numbers: 1 or 2 Optional 1D/2D DMA engine Internal or external to CPU core
Audio acceleration DSP extension Burst support for uncached load multiple Efficient atomic access synchronization without locking system bus Low-latency vectored interrupt for real-time performance Zero-wait-state local memory with 1D/2D DMA MMU HW page table walker TLB management instructions MPU memory protection regions
Flexibility Memory-mapped IO space PC-relative jumps for position independent code JTAG-based debug support Performance monitors for performance tuning Support for bi-endian data accesses Power Management Clock-gated pipeline Low-power mode support instructions
Applications
PMP Music player DVD Game DSC Storage Toys
AndesCore ™ Family: N9
Key Features
CPU Core
16/32bit mixable instruction format 16 or 32 general-purpose 32-bit registers 5-stage pipeline Multiply-add and multiply-subtract instructions Aligned post-increment load/store single Aligned and unaligned load/store multiple Vectored interrupts with 6 signals for interrupt sources and 2 runtime options: the built-in internal interrupt controller for 6 interrupt sources the external interrupt controller with 64 interrupt sources 2 or 3 HW nested interruption levels Memory-mapped I/O Non-Translated-Mapping (NTM) for cacheability attributes 4GB or 16MB address space
Memory Subsystem I & D cache
Virtually indexed and physically tagged Cache size: 4KB to 32KB Cache line size: 16B/32B Set associativity: direct or 2 way Cache locking support
External I & D local memory (LM)
Size: 1KB to 1MB
Bus Interface
APB/AHB/AHB-Lite or AMI (Andes Memory Interface)
Debug Support
JTAG debug interface Embedded debug module (EDM)
Benefit
Performance
16/32bit mixable instruction format for compacting code density Static branch predication Low-latency vectored interrupt for real-time performance Completion of one 32-bit operation per cycle
Flexibility Memory-mapped IO space PC-relative jumps for position independent code JTAG-based debug support Support for bi-endian data accesses Several configurations to trade off between core size and application requirements Power Management Clock-gated pipeline Power management instructions
Overview
16-/32-bit mixable instruction format
4/8-entry fully associative iTLB/dTLB
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